An integrated circuit (IC) typically comprises numerous semiconductor devices formed on a single crystal silicon substrate. The semiconductor devices can be transistors, diodes, etc. The semiconductor devices must be connected with each other using conductive lines for the IC to function. The conductive lines are effectively metal wires that allow electrical communication between the semiconductor devices. Newer ICs, and especially microprocessors, are becoming increasingly complex. Because of the increasing number of semiconductor devices found in newer ICs, the number of conductive lines needed to connect the devices is also increasing. For complex ICs, a single layer of conductive lines is insufficient. As a result, the conductive lines must be layered upon one another to create layers of metallization. In order to isolate the conductive lines an interlayer dielectric (ILD) is used. The ILD is an insulating layer, such as silicon dioxide (SiO.sub.2), which prevents shorts and unwanted communication between the conductive lines.
One way to fabricate layers of metallization for an IC involves using what is known as a damascene process. The first procedure of a damascene process is to deposit an ILD. An ILD is deposited either directly on a substrate, or on top of another existing layer of metallization. Once the ILD is deposited, portions of the ILD may be etched away to form recessed features, such as trenches and vias, which will accommodate the conductive lines. A trench can be created to accommodate an interconnect, which can connect different regions of the IC. A via can be created to accommodate either a via or a contact which will allow for communication between the interconnects of other layers or directly with the semiconductor devices in the substrate. A damascene process which creates either only trenches or vias is known as a single damascene process. A damascene process which creates both trenches and vias at once is known as a dual damascene process. In a dual damascene process, trenches and vias are created together.
After the recessed features are created, metal, such as copper or aluminum, is deposited in them to create the conductive lines. The deposition process typically deposits excess metal, which overfills the trenches and covers the entire surface of the ILD. The excess metal can be removed using a chemical mechanical polishing (CMP) process. The CMP process involves introducing a chemical slurry to the surface of the ILD while using a rotating polishing pad to remove excess metal and planarize the surface of the ILD.
Because feature sizes in ICs have recently become so small, the conductive lines in the layers of metallization are now separated by increasingly smaller gaps. An ILD comprises a dielectric material, which has a tendency to store charge, and can cause problems such as crosstalk and capacitive coupling between the conductive lines. A typical material used for ILDs is silicon dioxide (SiO2). Silicon dioxide has a dielectric constant (k) of approximately 4.0. With the reduction in feature size and subsequent reduction in distance between conductive lines, it has become desirable to use low-k dielectrics to reduce crosstalk and capacitive coupling. A low-k dielectric is typically defined as one that has a dielectric constant of less than that of SiO2, or of less than 4.0. Examples of low-k dielectrics include fluorosilicate glass (FSG) and carbon doped oxides (CDO).
One way to lower the dielectric constant (k) is to form pores in the dielectric material. For example, some dielectric materials use thermally activated porogens. When heat is applied, the porogen may decompose and/or volatilize, leaving pores in the dielectric material. For example, temperatures in the range of about 250 degrees C. to about 450 degrees C., which may be reached in dual damascene processing, may be used to thermally activate a porogen.
However, low-k dielectrics tend to be a mechanically weak, typically because they include pores or air pockets. Air pockets are created in a dielectric material in order to reduce the dielectric contestant because the dielectric constant (k) of air is approximately 1.0. The removal of material in order to create pores within an ILD results in a structurally weaker material, which may be damaged during processing. For example, the CMP process can typically cause cracks, shorts, and other deformities in the ILD. Using a low-k dielectric material may ultimately reduce product yields because of damage caused during processing.